Thumbnail
Ver/Abrir
Registro completo
Impacto
Google Scholar
Compartir
EmailLinkedinFacebookTwitter
Guarda la referencia
Mendely

Zotero

untranslated

Mets

Mods

Rdf

Marc

Exportar a BibTeX
Título
Static Current Unbalance of Paralleled SiC MOSFET Modules in the Final Layout
Autor-a
Autor-a (de otra institución)
Grupo de investigación
Accionamientos aplicados a la tracción y a la generación de energía eléctrica
Otras instituciones
Ikerlan
Versión
Postprint
Derechos
© 2020 IEEE
Acceso
Acceso abierto
URI
https://hdl.handle.net/20.500.11984/5800
Versión del editor
Publicado en
2020 IEEE Vehicle Power and Propulsion Conference (VPPC) 
Editor
IEEE
Palabras clave
MOSFET
Inductance
Silicon carbide
Layout ... [+]
MOSFET
Inductance
Silicon carbide
Layout
Logic gates
Gate drivers
Vehicle dynamics [-]
Resumen
Silicon Carbide (SiC) MOSFETs enable enhanced performance of power converters in several applications. Parallel connection of SiC MOSFETs become mandatory for medium power applications due to the curr ... [+]
Silicon Carbide (SiC) MOSFETs enable enhanced performance of power converters in several applications. Parallel connection of SiC MOSFETs become mandatory for medium power applications due to the current rate of existing modules. A balanced current sharing between paralleled MOSFETs is desired to maximize the power capability of each device, maximizing the power capability of the whole system. This work studies the static current unbalance of two paralleled 1200V-400A SiC MOSFET modules with individual gate driver. Experimental measurements are done focused on parasitic inductance caused by electromechanical layout. [-]
Sponsorship
Gobierno Vasco-Eusko Jaurlaritza
ID Proyecto
info:eu-repo/grantAgreement/GV/Elkartek 2019/KK-2019-00066/CAPV/Electrónica de potencia avanzada para la futura infraestructura del vehículo eléctrico/ELPIVE
Colecciones