Demystifying Non-Isolated DC–DC Topologies on Partial Power Processing Architectures

Abstract

This paper discusses the possibility of achieving partial power processing with non-isolated DC–DC topologies. To this end, partial power converter architectures are seen as an interesting solution for reducing the power processed by the converter. We observed via simulations that single-inductor non-isolated topologies cannot achieve partial power processing since the obtained current and voltage waveforms were the same as those found in a full-power converter. However, when using double inductor non-isolated topologies, reduced current and improved efficiencies were achieved. In order to confirm the results obtained from the simulations, single- and double-inductor topologies were tested experimentally. Finally, it was concluded that a double-inductor non-isolated topology can improve its performance by using partial power processing.