Partekatu
Gorde erreferentzia
Izenburua
Static Current Unbalance of Paralleled SiC MOSFET Modules in the Final Layout
Beste instituzio
IkerlanBertsioa
Postprinta
Eskubideak
© 2020 IEEESarbidea
Sarbide irekiaArgitaratzailearen bertsioa
https://doi.org/10.1109/VPPC49601.2020.9330969Non argitaratua
2020 IEEE Vehicle Power and Propulsion Conference (VPPC) Argitaratzailea
IEEEGako-hitzak
MOSFET
Inductance
Silicon carbide
Layout ... [+]
Inductance
Silicon carbide
Layout ... [+]
MOSFET
Inductance
Silicon carbide
Layout
Logic gates
Gate drivers
Vehicle dynamics [-]
Inductance
Silicon carbide
Layout
Logic gates
Gate drivers
Vehicle dynamics [-]
Laburpena
Silicon Carbide (SiC) MOSFETs enable enhanced performance of power converters in several applications. Parallel connection of SiC MOSFETs become mandatory for medium power applications due to the curr ... [+]
Silicon Carbide (SiC) MOSFETs enable enhanced performance of power converters in several applications. Parallel connection of SiC MOSFETs become mandatory for medium power applications due to the current rate of existing modules. A balanced current sharing between paralleled MOSFETs is desired to maximize the power capability of each device, maximizing the power capability of the whole system. This work studies the static current unbalance of two paralleled 1200V-400A SiC MOSFET modules with individual gate driver. Experimental measurements are done focused on parasitic inductance caused by electromechanical layout. [-]
