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Title
Static Current Unbalance of Paralleled SiC MOSFET Modules in the Final Layout
xmlui.dri2xhtml.METS-1.0.item-contributorOtherinstitution
https://ror.org/03hp1m080Version
http://purl.org/coar/version/c_ab4af688f83e57aa
Rights
© 2020 IEEEAccess
http://purl.org/coar/access_right/c_abf2Publisher’s version
https://doi.org/10.1109/VPPC49601.2020.9330969Published at
2020 IEEE Vehicle Power and Propulsion Conference (VPPC) Publisher
IEEEKeywords
MOSFET
Inductance
Silicon carbide
Layout ... [+]
Inductance
Silicon carbide
Layout ... [+]
MOSFET
Inductance
Silicon carbide
Layout
Logic gates
Gate drivers
Vehicle dynamics [-]
Inductance
Silicon carbide
Layout
Logic gates
Gate drivers
Vehicle dynamics [-]
Abstract
Silicon Carbide (SiC) MOSFETs enable enhanced performance of power converters in several applications. Parallel connection of SiC MOSFETs become mandatory for medium power applications due to the curr ... [+]
Silicon Carbide (SiC) MOSFETs enable enhanced performance of power converters in several applications. Parallel connection of SiC MOSFETs become mandatory for medium power applications due to the current rate of existing modules. A balanced current sharing between paralleled MOSFETs is desired to maximize the power capability of each device, maximizing the power capability of the whole system. This work studies the static current unbalance of two paralleled 1200V-400A SiC MOSFET modules with individual gate driver. Experimental measurements are done focused on parasitic inductance caused by electromechanical layout. [-]
