2026-04-11T05:21:41Zhttps://ebiltegia.mondragon.edu/oai/request

oai:ebiltegia.mondragon.edu:20.500.11984/63922024-10-07T09:38:54Zcom_20.500.11984_1143col_20.500.11984_1148

Arruti Romero, Asier Aizpuru, Iosu 2024-04-30T07:22:53Z 2024-04-30T07:22:53Z 2023 978-9-0758-1541-2 https://katalogoa.mondragon.edu/janium-bin/janium_login_opac.pl?find&ficha_no=174086 https://hdl.handle.net/20.500.11984/6392 This paper presents and evaluates a novel method for generating power losses on transistors avoiding high currents. These could heat up the circuit tracks, affecting the accurate thermal modeling of the system. The proposed procedure is based on the transistor current regulation with low gate voltages and the linearity between power and temperature, being useful for all transistor technologies (Si, SiC and GaN). Through this method, low DC currents are enough to bring transistors to their thermal limits. Thermal stability issues and their differences between technologies are discussed and an experimental validation of the method is carried out. eng © 2023 IEEE and EPE Association Device characterization Power losses Switching and conduction losses Junction temperature MOSFET Loss Measurement of Low RDS Devices Through Thermal Modelling - The Advantage of Not Turning it Fully On http://purl.org/coar/resource_type/c_c94f