<?xml version='1.0' encoding='UTF-8'?><?xml-stylesheet href='static/style.xsl' type='text/xsl'?><OAI-PMH xmlns="http://www.openarchives.org/OAI/2.0/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/ http://www.openarchives.org/OAI/2.0/OAI-PMH.xsd"><responseDate>2026-04-11T06:56:44Z</responseDate><request verb="GetRecord" identifier="oai:ebiltegia.mondragon.edu:20.500.11984/5914" metadataPrefix="rdf">https://ebiltegia.mondragon.edu/oai/request</request><GetRecord><record><header><identifier>oai:ebiltegia.mondragon.edu:20.500.11984/5914</identifier><datestamp>2024-07-12T08:22:47Z</datestamp><setSpec>com_20.500.11984_1143</setSpec><setSpec>col_20.500.11984_1148</setSpec></header><metadata><rdf:RDF xmlns:rdf="http://www.openarchives.org/OAI/2.0/rdf/" xmlns:ow="http://www.ontoweb.org/ontology/1#" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:ds="http://dspace.org/ds/elements/1.1/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:doc="http://www.lyncode.com/xoai" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/rdf/ http://www.openarchives.org/OAI/2.0/rdf.xsd">
   <ow:Publication rdf:about="oai:ebiltegia.mondragon.edu:20.500.11984/5914">
      <dc:title>Novel Analytical Method for Estimating the Junction-to-Top Thermal Resistance of Power MOSFETs</dc:title>
      <dc:creator>Arruti Romero, Asier</dc:creator>
      <dc:creator>Aizpuru, Iosu</dc:creator>
      <dc:contributor>Sanz-Alcaine, José Miguel</dc:contributor>
      <dc:contributor>Pérez-Cebolla, Francisco José</dc:contributor>
      <dc:contributor>Bernal Ruiz, Carlos</dc:contributor>
      <dc:subject>Semiconductor device modeling</dc:subject>
      <dc:subject>Temperature sensors</dc:subject>
      <dc:subject>Thermal resistance</dc:subject>
      <dc:subject>Surface resistance</dc:subject>
      <dc:subject>surface roughness</dc:subject>
      <dc:subject>Thermal analysis</dc:subject>
      <dc:subject>Rough surfaces</dc:subject>
      <dc:description>This papers proposes a new methodology for estimating the thermal resistance from the junction-to-top capsule surface. By placing the transistor in a vertical position, without being soldered to any PCB, and sensing the dissipated power and the temperatures of the device, it is possible to characterize the internal thermal resistance.</dc:description>
      <dc:date>2022-12-13T14:59:49Z</dc:date>
      <dc:date>2022-12-13T14:59:49Z</dc:date>
      <dc:date>2022</dc:date>
      <dc:type>http://purl.org/coar/resource_type/c_c94f</dc:type>
      <dc:identifier>978-9-0758-1539-9</dc:identifier>
      <dc:identifier>https://katalogoa.mondragon.edu/janium-bin/janium_login_opac.pl?find&amp;ficha_no=170433</dc:identifier>
      <dc:identifier>https://hdl.handle.net/20.500.11984/5914</dc:identifier>
      <dc:language>eng</dc:language>
      <dc:rights>© 2022 IEEE</dc:rights>
      <dc:publisher>IEEE</dc:publisher>
   </ow:Publication>
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