2026-04-11T09:28:39Zhttps://ebiltegia.mondragon.edu/oai/request

oai:ebiltegia.mondragon.edu:20.500.11984/58002024-03-04T14:51:50Zcom_20.500.11984_1143col_20.500.11984_1148

Garrido, David Baraia-Etxaburu, Igor 2022-11-03T08:46:08Z 2022-11-03T08:46:08Z 2020 978-1-7281-8959-8 1938-8756 https://katalogoa.mondragon.edu/janium-bin/janium_login_opac.pl?find&ficha_no=164701 https://hdl.handle.net/20.500.11984/5800 Silicon Carbide (SiC) MOSFETs enable enhanced performance of power converters in several applications. Parallel connection of SiC MOSFETs become mandatory for medium power applications due to the current rate of existing modules. A balanced current sharing between paralleled MOSFETs is desired to maximize the power capability of each device, maximizing the power capability of the whole system. This work studies the static current unbalance of two paralleled 1200V-400A SiC MOSFET modules with individual gate driver. Experimental measurements are done focused on parasitic inductance caused by electromechanical layout. eng © 2020 IEEE MOSFET Inductance Silicon carbide Layout Logic gates Gate drivers Vehicle dynamics Static Current Unbalance of Paralleled SiC MOSFET Modules in the Final Layout http://purl.org/coar/resource_type/c_c94f