2026-06-17T06:32:59Zhttps://ebiltegia.mondragon.edu/oai/request

oai:ebiltegia.mondragon.edu:20.500.11984/145352026-06-13T06:15:44Zcom_20.500.11984_1143com_20.500.11984_14090col_20.500.11984_1148

Alberdi Esuain, Borja Mazuela, Mikel San-Sebastian, Jon Sánchez, Roberto 2026-06-12T07:42:35Z 2026-06-12T07:42:35Z 2023 978-9-0758-1541-2 https://katalogoa.mondragon.edu/janium-bin/janium_login_opac.pl?find&ficha_no=174678 https://hdl.handle.net/20.500.11984/14535 This paper presents a comparative study of two analytical models for estimating the switching losses of a power MOSFET, considering different levels of parasitics integration. The study focuses on high parasitic inductance scenarios, where the models exhibit notable differences. The models are applied to predict the switching losses of a power MOSFET in a push-pull converter with a high power loop inductance value. The predicted results are validated through experimental testing, and the findings are discussed in detail. This study contributes to the understanding of the impact of parasitic elements on power MOSFET switching losses, and offers insights for optimizing the power converter design. eng © 2023 IEEE DC-DC converter Device modelling Hard switching Parasitic elements Power losses Switching losses estimation for a push-pull converter based on analytical models considering parasitic elements