An Experimentally Verified Behavioral GaN HD-GIT Transistor Model

Abstract

GaN HEMT transistors, with their superior on-resistance and switching times, provide a promising alternative to Si and SiC devices. Commercially available normally OFF GaN transistors can be categorized into two main groups: hybrid transistors, which incorporate a Si MOSFET, and e-mode transistors. The latter are the most promising GaN transistors, as they do not have the limitations of Si MOSFETs. Currently, there are two commercial e-mode transistors: the Schottky Gate (SG) p-GaN and the HD-GIT (Hybrid-Drain-embedded Gate Injection Transistor) transistors. However, they differ from the gate terminal standards that have been defined for years by Silicon IGBTs and MOSFETs (lower threshold voltage, non-constant Miller plateau, etc.), complicating their adoption in power electronics converters. This is particularly true for the HD-GIT transistor, which diverges from standard MOSFET gate operations due to its non-isolated gate terminal. To aid application engineers in understanding these devices and facilitating their adoption in real power applications, simulation models are useful tools. However, there are no simple HD-GIT transistor models that can be easily parameterized by application engineers. Therefore, in this work, an experimentally verified behavioral model of an HD-GIT transistor is presented and described.