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Título
Static Current Unbalance of Paralleled SiC MOSFET Modules in the Final LayoutFecha de publicación
2020Grupo de investigación
Accionamientos aplicados a la tracción y a la generación de energía eléctricaOtras instituciones
IkerlanVersión
PostprintTipo de documento
Contribución a congresoContribución a congresoIdioma
engDerechos
© 2020 IEEEAcceso
Acceso abiertoVersión de la editorial
https://doi.org/10.1109/VPPC49601.2020.9330969Publicado en
2020 IEEE Vehicle Power and Propulsion Conference (VPPC) Editorial
IEEEPalabras clave
MOSFET
Inductance
Silicon carbide
Layout ... [+]
Inductance
Silicon carbide
Layout ... [+]
MOSFET
Inductance
Silicon carbide
Layout
Logic gates
Gate drivers
Vehicle dynamics [-]
Inductance
Silicon carbide
Layout
Logic gates
Gate drivers
Vehicle dynamics [-]
Resumen
Silicon Carbide (SiC) MOSFETs enable enhanced performance of power converters in several applications. Parallel connection of SiC MOSFETs become mandatory for medium power applications due to the curr ... [+]
Silicon Carbide (SiC) MOSFETs enable enhanced performance of power converters in several applications. Parallel connection of SiC MOSFETs become mandatory for medium power applications due to the current rate of existing modules. A balanced current sharing between paralleled MOSFETs is desired to maximize the power capability of each device, maximizing the power capability of the whole system. This work studies the static current unbalance of two paralleled 1200V-400A SiC MOSFET modules with individual gate driver. Experimental measurements are done focused on parasitic inductance caused by electromechanical layout. [-]
Sponsorship
Gobierno Vasco-Eusko JaurlaritzaID Proyecto
info:eu-repo/grantAgreement/GV/Elkartek 2019/KK-2019-00066/CAPV/Electrónica de potencia avanzada para la futura infraestructura del vehículo eléctrico/ELPIVEColecciones
- Congresos - Ingeniería [432]
